At the NA Technology Symposium, TSMC SVP Kevin Zhang admitted that the firm will skip high-NA tools for its A14 node, instead sticking to tried and tested 0.33-NA EUV.

This U-turn gives Intel Foundry and some DRAM outfits a rare "technological" upper hand. Chipzilla s readying high-NA EUV for its 18A process next year while TSMC kicks the can down the road to A14P, somewhere around 2029.

Zhang said: "From 2 nanometers to A14, we don’t have to use high-NA, but we can continue to maintain similar complexity in terms of processing steps." Keeping mask counts low is the aim, apparently to prevent costs spiralling out of control.

The core issue is money. High-NA lithography would drive manufacturing costs up by 2.5 times, making A14 silicon expensive and harder to push into consumer products. Multiple masks per chip layer would simply add insult to injury.

Instead, TSMC is banking on 0.33-NA EUV plus multi-patterning wizardry to keep its chips complex but not wallet-melting. That keeps immediate costs down but risks letting competitors claim technical bragging rights.

Meanwhile, Samsung is preparing to take delivery of its first high-NA EUV tool next quarter, planning commercial use by late 2025. If TSMC sticks to its guns, it could be staring at a four-year gap behind Chipzilla and Samsung which is a rare stumble for the Taiwan giant.