Ironwood uses a dual-chiplet layout with a TensorCore running a systolic array for matrix grunt, a Vector Processing Unit for general AI chores and a Matrix Multiply Unit to keep throughput high. Each chiplet also houses two SparseCores for messy, irregular workloads such as embeddings that feed modern language models.

Each chip carries 96 GB of HBM, and the chiplets chat over a die-to-die link six times faster than a one-dimensional inter-chip connection. A rack holds 64 chips with 1.2 TB/s of bidirectional bandwidth to form a cube, and 9,216 chips across 144 cubes make a superpod stitched together with optical switching.

Google’s figures show the TPU v7 keeps pace with Nvidia gear on inference tasks while trimming the total cost of ownership, something that tends to grab the attention of budget hawks.

MediaTek built Ironwood’s input and output modules after Google moved that work away from Broadcom. UBS reckons the Taiwanese firm could bank $4 billion from the project, an impressive haul for work usually done behind the curtain.

Although the Dimensity 9600 is a very different creature from an ASIC, MediaTek can still pinch lessons. It can push more aggressive power gating for idle I/O blocks, tighten voltage scaling to cut energy draw and tweak clock gating to improve battery life. These gains matter because MediaTek has already scrapped efficiency cores from its mobile design.

The firm is also developing its own AI silicon, where Ironwood's experience will pay off in full. For now, the Dimensity 9600 seems set to gain enough TPU wisdom to boost its efficiency in a market where every watt counts.