Speaking to the gathered throngs its North American Technology Symposium, TSMC revealed that two quarters before mass production, defect density for the N2 node is already lower than it was for N3, N5, and even N7 at similar stages. This suggests TSMC is on track to start cranking out 2nm-class chips in late Q4 2025, as previously promised.

Despite ditching tried and tested FinFET transistors in favour of GAA, TSMC’s N2 defect rate has dropped sharply, following a trajectory similar to the more familiar N3/N3P nodes. Data presented at the event showed a steeper improvement curve than the older N7/N6 processes, although N5/N4 still had the most aggressive defect reduction early on.

TSMC said that production volume and a broad range of early tape-outs are helping it iron out kinks faster than usual. The company now has more customers using early N2 for smartphones and high-performance computing, giving engineers more chances to spot and fix problems. According to TSMC, this broader product mix is speeding up defect learning and process maturity.

The fact that defect rates for GAA are tracking alongside FinFET nodes is significant. Introducing a brand new transistor structure without faceplanting would normally be considered a miracle in chipmaking circles. Based on what TSMC is willing to show the public, the shift to GAAFETs is looking less like the trainwreck than many feared.

Of course, what TSMC shows noew and what happens when customers get their hands on real chips can sometimes be two very different stories.